1. Technical Field
The present invention relates generally to a self-aligned bipolar transistor, and more particularly, to a self-aligned bipolar transistor having a raised extrinsic base and methods of forming the transistor.
2. Related Art
Self-aligned bipolar transistors with Silicon-Germanium (SiGe) intrinsic base and doped polysilicon raised extrinsic base are the focus of integrated circuits fabricated for high performance mixed signal applications. The performance of self-aligned bipolar transistors with extrinsic base degrades as the emitter dimension is reduced due to loss of intrinsic base definition caused by the lateral diffusion of dopants. To maintain high electrical performance, new transistors must have a polysilicon extrinsic base layer self-aligned to the emitter on top of the epitaxy grown intrinsic SiGe base, i.e., a raised extrinsic base. Transistors fabricated using this approach have demonstrated the highest cutoff frequency (Ft) and maximum oscillation frequency (Fmax) to date.
FIG. 1 shows a prior art transistor 10 with a raised extrinsic base 12 having a uniform lateral doping profile. A key performance feature of transistor 10 is the epitaxy grown intrinsic SiGe base 20 that contains the intrinsic portion of the base dopant. The Ge/Si ratio, doping level, and film thickness of the intrinsic base are primary factors in the emitter to collector transit time and corresponding Ft. Another key performance feature of transistor 10 is self-alignment, i.e., the spacing between extrinsic base 12 polysilicon to an emitter 14 polysilicon determined by sidewall spacer 16 rather than lithography (i.e. non-self-aligned). The small spacing is required to lower the base resistance component underneath spacer 16 to maintain a high Fmax.
A few different methods of forming a self-aligned bipolar transistor with raised polysilicon extrinsic base have been implemented. In one method, chemical mechanical polishing (CMP) is used to planarize the extrinsic base polysilicon over a pre-defined sacrificial emitter pedestal as described in U.S. Pat. Nos. 5,128,271 and 6,346,453. In this approach, an extrinsic base of area A and depth D has a low aspect ratio (D/A<<1), which can lead to a significant difference in the extrinsic base layer thickness between small and large devices, as well as isolated versus nested devices, due to dishing caused by the CMP. In another approach, an intrinsic base is grown using selective epitaxy inside an emitter opening and an undercut is formed under the extrinsic base polysilicon, as described in U.S. Pat. Nos. 5,494,836, 5,506,427, and 5,962,880. In this approach, the self-alignment of the extrinsic base is achieved with the epitaxial growth inside the undercut. In this case, special techniques are required to ensure a good link-up contact between the intrinsic base and the extrinsic base. Each of these approaches has significant process and manufacturing complexity.
In view of the foregoing, there is a need in the art for an improved self-aligned transistor with a raised extrinsic base and improved method of fabricating such a transistor that do not suffer from the problems of the related art.